The Magic of RISC-V Vector Processing

Back in the middle 70s Seymour Cray invented pipelined vector processing and implemented it in his eponymous supercomputer hardware, along with vector registers.

Intel implemented 128 bit vector floating point SSE instructions and registers around 1999. By 2008 they had proposed AVX 256 bit registers and instructions. These features shipped in 2011 for Intel, and soon after for AMD. Next up for x86 architectures were the AVX512 extensions.

Yes, the RISC V architecture has vector extensions now as well, and I'm sure ARM has them too. But they're just playing catch-up with Intel, who copied Seymour Cray.

BTW, back in the day, I had access to an early SUN Microsystems SPARC "RISC" computer. In those days, "RISC" meant every instruction would complete in a single clock cycle, and there would be no hidden internal states such as pipelines. There was no hardware integer divide; it was unrolled in software. And integer multiply was implemented as two or three "multiply helper" instructions, each completing in a single clock. Ideas like re-order buffers, register re-naming, and pipelines were anathema to the early RISC designers. How times change!!